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Autor
Mutanga Alfred (University of Venda, University Road, Thohoyandou, South Africa)
Tytuł
A SystemC Cache Simulator for a Multiprocessor Shared Memory System
Źródło
International Letters of Social and Humanistic Sciences (ILSHS), 2014, vol. 2, s. 75-87, rys., tab., bibliogr. 27 poz.
Słowa kluczowe
Informatyka, Systemy komputerowe
Information science, Computer systems
Uwagi
summ.
Abstrakt
In this research we built a SystemC Level-1 data cache system in a distributed shared memory architectural environment, with each processor having its own local cache. Using a set of Fast-Fourier Transform and Random trace files we evaluated the cache performance, based on the number of cache hits/misses, of the caches using snooping and directory-based cache coherence protocols. A series of experiments were carried out, with the results of the experiments showing that the directory-based MOESI cache coherency protocol has a performance edge over the snooping Valid-Invalid cache coherency protocol. (original abstract)
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Bibliografia
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  11. Jesshope C. R. (2008). A model for the design and programming of multi-cores. In: GRANDINETTI, L. (ed.) Advances in Parallel Computing, 16, High performance Computing and Grids in Action London: IOS Press.
  12. Jesshope C. R. (2009). Multiprocessor Memory Systems, Amsterdam Universiteit van Amsterdam.
  13. Jesshope C. R .(2011). A SystemC Tutorial. Amsterdam, Universiteit van Amsterdam.
  14. Joubert G. R. (2008). "Parallel computing current and future issues of high end computing", Forschungszentrum, John von Neumann Institute for Computing Jülich.
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  16. Ma N., "Modelling and evaluation of multi-core multithreaded processor architectures in SystemC", Proquest, (2011) 1109.
  17. Mckee A. S. (2004). Reflections on the Memory Wall. In: ACM, ed. Proceedings of the 1st conference on Computing frontiers (CF '04). 2004 New York. New York: ACM, 1-6.
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  19. OSCI. (2005). An Introduction to System Level Modelling in SystemC 2.0. Available: www.es.ele.tue.nl/~heco/courses/EmbSystems/WhitePaper20.pdf [Accessed 15 March 2013].
  20. Panesar G. T. D., Duller A., Gray A., Robins W. (2005). Deterministic Parallel Processing. In: BROENIK, J., F. AND HILDERINK, G. (ed.) Microgrid workshop- 2005. London: IOS Press.
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  22. PICOCHIP. (2007). Technical White Paper: Practical, Programmable Multi-Core DSP. Available: http://www.picochip.com/downloads/4eac6c97aa70840ad7f4d12aec82ebf1/Multicore_June_2007.pdf [Accessed 13 March 2013].
  23. Schintke F., Simon J., Reinfield A. (2012). A Cache Simulator for Shared Memory Systems (unpublished paper).
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  27. Towner D. P. G., Duller A., Gray A., Robins W. (2004). Debugging and Verification of Parallel Systems - the picoChip way! In: BROENIK, J., F. AND HILDERINK, G. (ed.) Communicating Process Architectures London: IOS Press.
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ISSN
2300-2697
Język
eng
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